module clok_div_1hz(clk_1khz,clk_1hz,rst);
/*
 *实现1khz -> 1hz 分频
 *实现1000分频
 */
 
	input clk_1khz;
	input rst;
	output reg clk_1hz;
	reg[9:0] cnt_1hz;
	 
	 //1khz -> 1hz 1000 10000/2 - 1分频
	always @(posedge clk_1khz or negedge rst)
		 if(!rst) begin
			  cnt_1hz <= 9'b000000000;
			  clk_1hz <= 1'b0;
		 end
		 else if(cnt_1hz < 9'b1_1111_0011) begin
			  cnt_1hz <= cnt_1hz + 1'b1;
		 end
		 else begin
			  cnt_1hz <= 9'b000000000;
			  clk_1hz <= ~clk_1hz;
		 end
		 
endmodule